// IF/ID

// Naming convention for wires out
// of this register should be [wirename]0

// In/Out Parameters with # of bits:
//    PC = 32
//    Instruction = 32
//    AdderA = 32

module Fetch_Decode(CLK,
                    PCIn,
                    PCOut,
                    InstructionIn,
                    InstructionOut,
                    AdderAIn,
                    AdderAOut,
                    Flush);

  input CLK, Flush;    
  input [31:0] PCIn, InstructionIn,AdderAIn;

  output [31:0] PCOut, InstructionOut,AdderAOut;
  
  reg [31:0] PCOut, InstructionOut,AdderAOut;

  always @(negedge CLK)
    if(Flush)
      begin
        PCOut <= 0;
        InstructionOut <= 4294967295;
        AdderAOut <= 0;
      end
    else
      begin
        PCOut <= PCIn;
        InstructionOut <= InstructionIn;
        AdderAOut <= AdderAIn;
      end
endmodule
